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1 features ? 16-mbit (x16) flash and 8-mbit psram 2.7v to 3.3v operating voltage low operating power ? 27 ma operating current ? 53 a standby current extended temperature range flash 2.7v to 3.3v read/write access time ? 70 ns sector erase architecture ? thirty-one 32k word (64k byte) sectors with individual write lockout ? eight 4k word (8k byte) sectors with individual write lockout fast word program time ? 12 s suspend/resume feature for erase and program ? supports reading and programming from any sector by suspending erase of a different sector ? supports reading any word by suspending programming of any other word low-power operation ?12 ma active ? 13 a standby data polling, toggle bit, ready/busy for end of program detection vpp pin for write protection and accelerated program/erase operations reset input for device initialization sector lockdown support top/bottom boot block configuration 128-bit protection register minimum 100,000 erase cycles psram 8-mbit (512k x 16) 2.7v to 3.3v v cc operating voltage 70 ns access time fully static operation and tri-state output isb0 < 10 a when deep power-down device number flash configuration psram configuration at52bc1661a(t) 16m (1m x 16) 8m (512k x 16) 16-mbit flash + 8-mbit psram stack memory at52bc1661a at52bc1661at preliminary rev. 3455a?stkd?11/04
2 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 cbga top view pin configurations a14 a9 i/o11 a6 a0 a b c d e f g h 3 45678910 a15 a10 a19 poe a7 a4 a13 i/o15 i/o13 i/o12 i/o9 a3 ce a12 pwe i/o6 zz i/o10 i/o8 a2 gnd gnd i/o14 i/o4 pvcc i/o2 i/o0 a1 oe nc i/o7 i/o5 vcc i/o3 i/o1 pcs1 nc nc a16 we pgnd nc plb a18 nc a11 a8 rdy busy reset vpp pub a17 a5 nc nc nc nc nc nc nc nc 1 2 11 12 pin name function a0 - a18, a19 common address input for 8m psram/flash, flash address input ce flash chip enable oe /poe flash/psram, output enable we /pwe flash/psram, write enable vcc flash power supply vpp optional flash power supply for faster program/erase operations i/o0-i/o15 data inputs/outputs pcs1 psram chip select rdy/busy flash ready/busy output pvcc psram power supply gnd/pgnd flash/psram gnd pub psram upper byte plb psram lower byte nc no connect reset flash reset zz low-power modes
3 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 description the at52bc1661a(t) combines a single 16-mbit flash and a 8-mbit psram: both of the devices are offered in a stacked 66-ball cbga package. the devices operate at 2.7v to 3.3v in the extended temperature range. block diagram absolute maximum ratings temperature under bias................................... -25 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -55 c to +150 c all input voltages except v pp (including nc pins) with respect to ground .............................-0.2v to v cc + 0.3v voltage on v pp with respect to ground ..................................-0.2v to + 12.5v all output voltages with respect to ground .............................-0.2v to v cc + 0.3v flash psram address data reset ce rdy/busy pcs1 zz pub plb we oe pwe poe dc and ac operating range at52bc1661a(t)-70 operating temperature (case) extended -25 c to 85 c v cc power supply 2.7v to 3.3v
4 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 16-mbit flash memory block diagram identifier register status register data comparator output multiplexer output buffer input buffer command register data register y-gating write state machine program/erase voltage switch ce we oe reset rdy/busy vpp vcc gnd y-decoder x-decoder input buffer address latch i/o0 - i/o15 a0 - a19 main memory
5 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 16-mbit flash description the 16-mbit flash is organized as 1,048,576 words of 16 bits each. the x16 data appears on i/o0 - i/o15. the memory is divided into 39 sectors for erase operations. the device has ce and oe control signals to avoid any bus contention. this device can be read or reprogrammed using a single power supply, making it ideally suited for in-system programming. the device powers on in the read mode. command sequences are used to place the device in other operation modes such as program and erase. the device has the capability to protect the data in any sector (see ?sector lockdown? section). to increase the flexibility of the device, it contains an erase suspend and program suspend feature. this feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory. the end of a program or an erase cycle is detected by the ready/busy pin, data polling or by the toggle bit. the vpp pin provides data protection. when the v pp input is below 0.4v, the program and erase functions are inhibited. when v pp is at 0.9v or above, normal program and erase opera- tions can be performed. a six-byte command (enter single pulse program mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. after entering the six-byte code, only single pul ses on the write control lines are required for writing into the device. this mode (single pu lse word program) is exited by powering down the device, or by pulsing the reset pin low for a minimum of 500 ns and then bringing it back to v cc . erase, erase suspend/resume and program suspend/resume commands will not work while in this mode; if entered they will result in data being programmed into the device. it is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code. device operation read: the flash is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins are asserted on the out- puts. the outputs are put in the high impedance state whenever ce or oe is high. this dual- line control gives designers flexibility in preventing bus contention. command sequences: when the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. in order to perform other device functions, a series of command sequences are entered into the device. the command sequences are shown in the ?command definition in hex? table on page 13 (i/o8 - i/o15 are don?t care inputs for the command codes). the command sequences are written by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . standard microprocessor write timings are used. the address locations used in the command sequences are not affected by entering the command sequences. reset: a reset input pin is provided to ease some system applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset input halts the present device operation and puts the outputs of the device in a high impedance state. when a high level is reasserted on the reset pin, the device returns to the read or standby mode, depending upon the state of the control inputs.
6 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 erasure: before a word can be reprogrammed, it must be erased. the erased state of memory bits is a logical ?1?. the entire device can be erased by using the chip erase com- mand or individual sectors can be erased by using the sector erase command. chip erase: the entire device can be erased at one time by using the six-byte chip erase software code. after the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. the maximum time to erase the chip is t ec . if the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unp rotected sectors. after the chip erase, the device will return to the read or standby mode. sector erase: as an alternative to a full chip erase, the device is organized into 39 sec- tors (sa0 - sa38) that can be individually erased. the sector erase command is a six-bus cycle operation. the sector address is latched on the falling we edge of the sixth cycle while the 30h data input command is latched on the rising edge of we . the sector erase starts after the rising edge of we of the sixth cycle. the erase operati on is internally controlled; it will automatically time to completion. the maximum time to erase a sector is t sec . when the sec- tor programming lockdown feature is not enabled, the sector will erase (from the same sector erase command). an attempt to erase a sector that has been protected will result in the oper- ation terminating immediately. word programming: once a memory block is erased, it is programmed (to a logical ?0?) on a word-by-word basis. programming is accomplished via the internal device command reg- ister and is a four-bus cycle operation. the device will automatically generate the required internal program pulses. any commands written to the chip during the embedded programming cycle will be ignored. if a hardware reset happens during programming, the data at the location being programmed will be corrupted. please note that a data ?0? cannot be programmed back to a ?1?; only erase operations can convert ?0?s to ?1?s. programming is completed after the specified t bp cycle time. the data polling feature or the toggle bit feature may be used to indicate the end of a program cycle. if the erase/program status bit is a ?1?, the device was not able to verify that the erase or program operation was performed successfully. vpp pin: the circuitry of the device is designed so that it cannot be programmed or erased if the v pp voltage is less that 0.4v. when v pp is at 0.9v or above, normal program and erase operations can be performed. the vpp pin cannot be left floating. program/erase status: the device provides several bits to determine the status of a program or erase operation: i/o2, i/o3, i/o5, i/o6 and i/o7. the ?status bit table? on page 12 and the following four sections describe the function of these bits. to provide greater flexibility for system designers, the flash contains a programmable configuration register. the configu- ration register allows the user to specify the status bit operation. the configuration register can be set to one of two different values, ?00? or ?01?. if the configuration register is set to ?00?, the part will automatically return to the read mode after a successful program or erase operation. if the configuration register is set to a ?01?, a product id exit command must be given after a successful program or erase operation before the part will return to the read mode. it is impor- tant to note that whether the configuration register is set to a ?00? or to a ?01?, any unsuccessful program or erase operation requires using the product id exit command to return the device to read mode. the default value (after power-up) for the configuration regis- ter is ?00?. using the four-bus cycle set configuration register command as shown in the ?command definition in hex? table on page 13, the value of the configuration register can be changed. voltages applied to the reset pin will not alter the value of the configuration regis- ter. the value of the configuration register will affect the operation of the i/o7 status bit as described below.
7 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 data polling: the 16-mbit flash features data polling to indicate the end of a program cycle. if the status configuration register is set to a ?00?, during a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. during a chip or sector erase operation, an attempt to read the device will give a ?0? on i/o7. once the program or erase cycle has completed, true data will be read from the device. data polling may begin at any time during the program cycle. please see ?status bit table? on page 12 for more details. if the status bit configuration register is set to a ?01?, the i/o7 status bit will be low while the device is actively programming or erasing dat a. i/o7 will go high when the device has com- pleted a program or erase operation. once i/o7 has gone high, status information on the other pins can be checked. the data polling status bit must be used in conjunction with the erase/program and v pp status bit as shown in the algorithm in figures 1 and 2 on page 10. toggle bit: in addition to data polling the device provides another method for determining the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the memory will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examin- ing the toggle bit may begin at any time during a program cycle. please see ?status bit table? on page 12 for more details. the toggle bit status bit should be used in conjunction with the erase/program and v pp status bit as shown in the algorithm in figures 3 and 4 on page 11. erase/program status bit: the device offers a status bit on i/o5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. if the status bit is a ?1?, the device is unable to verify that an erase or a word program operation has been successfully performed. if a program (sector erase) command is issued to a pro- tected sector, the protected sector will not be programmed (erased). the device will go to a status read mode and the i/o5 status bit will be set high, indicating the program (erase) opera- tion did not complete as requested. once the erase/program status bit has been set to a ?1?, the system must write the product id exit command to return to the read mode. the erase/program status bit is a ?0? while the erase or program operation is still in progress. please see ?status bit table? on page 12 for more details. v pp status bit: the device provides a status bit on i/o3, which provides information regarding the voltage level of the vpp pin. during a program or erase operation, if the voltage on the vpp pin is not high enough to perform the desired operation successfully, the i/o3 sta- tus bit will be a ?1?. once the v pp status bit has been set to a ?1?, the system must write the product id exit command to return to the read mode. on the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the v pp status bit will out- put a ?0?. please see ?status bit table? on page 12 for more details. sector lockdown: each sector has a programming lockdown feature. this feature pre- vents programming of data in the designated sectors once the feature has been enabled. these sectors can contain secure code that is used to bring up the system. enabling the lock- down feature will allow the boot code to stay in the device while data in the rest of the device is updated. this feature does not have to be activated; any sector?s usage as a write-protected region is optional to the user.
8 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 at power-up or reset, all sectors are unlocked. to activate the lockdown for a specific sector, the six-bus cycle sector lockdown command must be issued. once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed. sector lockdown detection: a software method is available to determine if program- ming of a sector is locked down. when the devic e is in the software product identification mode (see ?software product identification entry/exit? sections on page 23), a read from address location 00002h within a sector will show if programming the sector is locked down. if the data on i/o0 is low, the sector can be programmed; if the data on i/o0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. the software product identification exit code should be used to return to standard operation. sector lockdown override: the only way to unlock a sector that is locked down is through reset or power-up cycles. after power-up or reset, the content of a sector that is locked down can be erased and reprogrammed. erase suspend/erase resume: the erase suspend command allows the system to interrupt a sector or chip erase operation and then program or read data from a different sector within the memory. after the erase suspend co mmand is given, the device requires a maxi- mum time of 15 s to suspend the erase operation. after the erase operation has been suspended, the system can then read data or program data to any other sector within the device. an address is not required during the erase suspend command. during a sector erase suspend, another sector cannot be erased. to resume the sector erase operation, the system must write the erase resume command. the erase resume command is a one-bus cycle command. the device also supports an erase suspend during a complete chip erase. while the chip erase is suspended, the user can read from any sector within the memory that is pro- tected. the command sequence for a chip erase suspend and a sector erase suspend are the same. program suspend/program resume: the program suspend command allows the system to interrupt a programming operation an d then read data from a different word within the memory. after the program suspend command is given, the device requires a maximum of 20 s to suspend the programming operati on. after the programming operation has been suspended, the system can then read data from any other word that is not contained in the sector in which the programming operation was suspended. an address is not required during the program suspend operation. to resume the programming operation, the system must write the program resume command. the program suspend and resume are one-bus cycle com- mands. the command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same. product identification: the product identification mode identifies the device and man- ufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the atmel product. for details, see ?operating modes? on page 16 (for hardware operation) or ?software product identification entry/exit? sections on page 23. the manufacturer and device codes are the same for both modes. 128-bit protection register: the device contains a 128-bit register that can be used for security purposes in system design. the protection register is divided into two 64-bit blocks. the two blocks are designated as block a and block b. the data in block a is non-changeable and is programmed at the factory with a unique number. the data in block b is programmed by the user and can be locked out such that data in the block cannot be repro- grammed. to program block b in the protection register, the four-bus cycle program protection register command must be used as shown in the ?command definition in hex? table on page 13. to lock out block b, the four-bus cycle lock protection register command
9 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 must be used as shown in the ?command definiti on in hex? table. data bit d1 must be zero during the fourth bus cycle. all other data bits during the fourth bus cycle are don?t cares. to determine whether block b is locked out, the product id entry command is given followed by a read operation from address 80h. if data bit d1 is zero, block b is locked. if data bit d1 is one, block b can be reprogrammed. please see the ?flash protection register addressing table? on page 13 for the address locations in the protection register. to read the protection register, the product id entry command is given followed by a normal read operation from an address within the protection register. after determining whether block b is protected or not, or reading the protection register, the product id exit command must be given prior to performing any other operation. rdy/busy : for the 16-mbit flash, an open-drain ready/busy output pin provides another method of detecting the end of a program or erase operation. rdy/busy is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. the open-drain connection allows for or-tying of several devices to the same rdy/busy line. please see ?status bit table? on page 12 for more details. hardware data protection: the hardware data protecti on feature protects against inadvertent programs to the device in the following ways: (a) v cc sense: if v cc is below 1.8v (typical), the program function is inhibited. (b) v cc power-on delay: once v cc has reached the v cc sense level, the device will automatically time out 10 ms (typical) before programming. (c) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (d) program inhibit: v pp is less than v ilpp . (e) v pp power-on delay: once v pp has reached 1.65v, program and erase operations are inhibited for 100 ns. input levels: while operating with a 2.7v to 3.3v power supply, the address inputs and control inputs (oe , ce and we ) may be driven from 0 to 5.5v without adversely affecting the operation of the device. the i/o lines can only be driven from 0 to v cc + 0.3v.
10 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 figure 1. data polling algorithm (configuration register = 00) notes: 1. va = valid address for programming. during a sec- tor erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. i/o7 should be rechecked even if i/o5 = ?1? because i/o7 may change simultaneously with i/o5. start read i/o7 - i/o0 addr = va i/o7 = data? i/o3, i/o5 = 1? read i/o7 - i/o0 addr = va i/o7 = data? program/erase operation not successful, write product id exit command no no no yes yes yes program/erase operation successful, device in read mode figure 2. data polling algorithm (configuration register = 01) note: 1. va = valid address for programming. during a sec- tor erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o3, i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful, write product id exit command no no no yes yes yes
11 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 figure 3. toggle bit algorithm (configuration register = 00) note: 1. the system should recheck the toggle bit even if i/o5 = ?1? because the toggle bit may stop toggling as i/o5 changes to ?1?. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o3, i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful, device in read mode no no no yes yes yes figure 4. toggle bit algorithm (configuration register = 01) note: 1. the system should recheck the toggle bit even if i/o5 = ?1? because the toggle bit may stop toggling as i/o5 changes to ?1?. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o3, i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful, write product id exit command no no no yes yes yes
12 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 notes: 1. i/o5 switches to a ?1? when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. 2. i/o3 switches to a ?1? when the v pp level is not high enough to successfully perform program and erase operations. status bit table status bit i/o7 i/o7 i/o6 i/o5 (1) i/o3 (2) i/o2 rdy/busy configuration register 00 01 00/01 00/01 00/01 00/01 00/01 programming i/o7 0toggle0010 erasing 0 0 toggle 0 0 toggle 0 erase suspended & read erasing sector 11100toggle1 erase suspended & read non-erasing sector data data data data data data 1 erase suspended & program non-erasing sector i/o7 0 toggle 0 0 toggle 0 erase suspended & program suspended and reading from non- suspended sectors data data data data data data 1 program suspended & read programming sector i/o71100toggle1 program suspended & read non-programming sector data data data data data data 1
13 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 notes: 1. the data format shown for each bus cycle is as follows; i/o7 - i/o0 (hex). i/o15 - i/o8 are don?t care. the address for mat shown for each bus cycle is as follows: a11 - a0 (hex). address a19 through a11 are don?t care. 2. since a11 is a don?t care, aaa can be replaced with 2aa. 3. sa = sector address. any word address within a sector c an be used to designate the sector address (see pages 14 - 16 for deta ils). 4. once a sector is in the lockdown mode, data in the protecte d sector cannot be changed unless the chip is reset or power cycle d. 5. either one of the product id exit commands can be used. 6. if data bit d1 is ?0?, block b is locked. if data bit d1 is ?1?, block b can be reprogrammed. 7. the default state (after power-up) of the configuration register is ?00?. 8. bytes of data other than f0 may be used to exit the product id mode. however, it is recommended that f0 be used. 9. this fast programming option enables the user to program two words in parallel only when v pp = 12v. the addresses, addr1 and addr2, of the two words, d in1 and d in2 , must only differ in address a0. this command should be used during manufacturing purposes only. note: all address lines not specified in the above table must be ?0? when accessing the protection register, i.e., a19 - a8 = 0. command definition in hex (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 555 aa aaa (2) 55 555 80 555 aa aaa 55 555 10 sector erase 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (3)(4) 30 word program 4 555 aa aaa 55 555 a0 addr d in dual word program (9) 5 555 aa aaa 55 555 e0 addr1 d in1 addr2 d in2 enter single pulse program mode 6 555 aa aaa 55 555 80 555 aa aaa 55 555 a0 single pulse word program 1addrd in sector lockdown 6 555 aa aaa (2) 55 555 80 555 aa aaa 55 sa (3)(4) 60 erase/program suspend 1 xxx b0 erase/program resume 1 xxx 30 product id entry 3 555 aa aaa 55 555 90 product id exit (5) 3 555 aa aaa 55 555 f0 (8) product id exit (5) 1 xxx f0 (8) program protection register 4 555 aa aaa 55 555 c0 addr d in lock protection register - block b 4 555 aa aaa 55 555 c0 080 x0 status of block b protection 4 555 aa aaa 55 555 90 80 d out (6) set configuration register 4 555 aa aaa 55 555 d0 xxx 00/01 (7) cfi query 1 x55 98 flash protection register addressing table word use block a7 a6 a5 a4 a3 a2 a1 a0 0 factory a 10000001 1 factory a 10000010 2 factory a 10000011 3 factory a 10000100 4 user b 10000101 5 user b 10000110 6 user b 10000111 7 user b 10001000
14 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 bottom boot? sector address table sector size (words) x16 address range (a19 - a0) sa0 4k 00000 - 00fff sa1 4k 01000 - 01fff sa2 4k 02000 - 02fff sa3 4k 03000 - 03fff sa4 4k 04000 - 04fff sa5 4k 05000 - 05fff sa6 4k 06000 - 06fff sa7 4k 07000 - 07fff sa8 32k 08000 - 0ffff sa9 32k 10000 - 17fff sa10 32k 18000 - 1ffff sa11 32k 20000 - 27fff sa12 32k 28000 - 2ffff sa13 32k 30000 - 37fff sa14 32k 38000 - 3ffff sa15 32k 40000 - 47fff sa16 32k 48000 - 4ffff sa17 32k 50000 - 57fff sa18 32k 58000 - 5ffff sa19 32k 60000 - 67fff sa20 32k 68000 - 6ffff sa21 32k 70000 - 77fff sa22 32k 78000 - 7ffff sa23 32k 80000 - 87fff sa24 32k 88000 - 8ffff sa25 32k 90000 - 97fff sa26 32k 98000 - 9ffff sa27 32k a0000 - a7fff sa28 32k a8000 - affff sa29 32k b0000 - b7fff sa30 32k b8000 - bffff sa31 32k c0000 - c7fff sa32 32k c8000 - cffff sa33 32k d0000 - d7fff sa34 32k d8000 - dffff sa35 32k e0000 - e7fff sa36 32k e8000 - effff sa37 32k f0000 - f7fff sa38 32k f8000 - fffff
15 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 top boot? sector address table sector size (words) x16 address range (a19 - a0) sa0 32k 00000 - 07fff sa1 32k 08000 - 0ffff sa2 32k 10000 - 17fff sa3 32k 18000 - 1ffff sa4 32k 20000 - 27fff sa5 32k 28000 - 2ffff sa6 32k 30000 - 37fff sa7 32k 38000 - 3ffff sa8 32k 40000 - 47fff sa9 32k 48000 - 4ffff sa10 32k 50000 - 57fff sa11 32k 58000 - 5ffff sa12 32k 60000 - 67fff sa13 32k 68000 - 6ffff sa14 32k 70000 - 77fff sa15 32k 78000 - 7ffff sa16 32k 80000 - 87fff sa17 32k 88000 - 8ffff sa18 32k 90000 - 97fff sa19 32k 98000 - 9ffff sa20 32k a0000 - a7fff sa21 32k a8000 - affff sa22 32k b0000 - b7fff sa23 32k b8000 - bffff sa24 32k c0000 - c7fff sa25 32k c8000 - cffff sa26 32k d0000 - d7fff sa27 32k d8000 - dffff sa28 32k e0000 - e7fff sa29 32k e8000 - effff sa30 32k f0000 - f7fff sa31 4k f8000 - f8fff sa32 4k f9000 - f9fff sa33 4k fa000 - fafff sa34 4k fb000 - fbfff sa35 4k fc000 - fcfff sa36 4k fd000 - fdfff sa37 4k fe000 - fefff sa38 4k ff000 - fffff
16 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms on page 21. 3. v h = 12.0v 0.5v. 4. manufacturer code: 001fh, device code: 00c0h ? bottom boot, 00c2h, top boot. 5. see details under ?software product identification entry/exit? on page 23. 6. v ihpp (min) = 0.9v; v ihpp (max) = 3.6v. 7. v ilpp (max) = 0.4v. dc and ac operating range 16-mbit flash-70 operating temperature (case) extended -25c to 85c v cc power supply 2.70v to 3.3v operating modes mode ce oe we reset v pp ai i/o read v il v il v ih v ih xaid out program/erase (2) v il v ih v il v ih v ihpp (6) ai d in standby/program inhibit v ih x (1) xv ih x x high-z program inhibit xxv ih v ih x xv il xv ih x xxx v ih v ilpp (7) output disable x v ih xv ih x high-z reset xxx v il x x high-z product identification hardware v il v il v ih v ih a1 - a19 = v il , a9 = v h (3) , a0 = v il manufacturer code (4) a1 - a19 = v il , a9 = v h (3) , a0 = v ih device code (4) software (5) v ih a0 = v il , a1 - a19 = v il manufacturer code (4) a0 = v ih , a1 - a19 = v il device code (4)
17 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 note: 1. in the erase mode, i cc is 45 ma. dc characteristics symbol parameter condition min typ max units i li input load current v in = 0v to v cc 2a i lo output leakage current v i/o = 0v to v cc 10 a i sb v cc standby current cmos ce = v cc - 0.3v to v cc 13 25 a i cc (1) v cc active read current f = 5 mhz; i out = 0 ma 12 25 ma i cc1 v cc programming current 40 ma i pp1 v pp input load current 5a v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol1 output low voltage i ol = 2.1 ma 0.45 v v ol2 output low voltage i ol = 1.0 ma 0.20 v v oh1 output high voltage i oh = -400 a 2.4 v v oh2 output high voltage i oh = -100 a 2.5 v
18 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce , whichever occurs first (cl = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read characteristics symbol parameter 16-mbit flash-70 units min max t rc read cycle time 70 ns t acc address to output delay 70 ns t ce (1) ce to output delay 70 ns t oe (2) oe to output delay 0 20 ns t df (3)(4) ce or oe to output float 0 25 ns t oh output hold from oe , ce or address, whichever occurred first 0 ns t ro reset to output delay 100 ns output valid output high z reset oe toe tce address valid tdf toh tacc tro ce address trc
19 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 input test waveforms and measurement level t r , t f < 5 ns output test load note: this parameter is characterized and is not 100% tested. cl (1) 1029 ohm 1728 ohm 2.8v = v tm pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
20 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 ac word load waveforms we controlled ce controlled ac word load characteristics symbol parameter min max units t as , t oes address, oe setup time 0 ns t ah address hold time 35 ns t cs chip select setup time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )35ns t ds data setup time 35 ns t dh , t oeh data, oe hold time 0 ns t wph write pulse width high 35 ns
21 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 program cycle waveforms sector or chip erase cycle waveforms notes: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 555. for sector erase, the address depends on what sector is to be erased. (see note 3 under ?command definitions in hex? on page 13.) 3. for chip erase, the data should be 10h, and for sector erase, the data should be 30h. program cycle characteristics symbol parameter min typ max units t bp word programming time 12 200 s t bpd word programming time in dual programming mode 6 100 s t as address setup time 0ns t ah address hold time 35 ns t ds data setup time 35 ns t dh data hold time 0ns t wp write pulse width 35 ns t wph write pulse width high 35 ns t wc write cycle time 70 ns t rp reset pulse width 500 ns t ec chip erase cycle time 25 seconds t sec1 sector erase cycle time (4k word sectors) 3.0 seconds t sec2 sector erase cycle time (32k word sectors) 5.0 seconds t es erase suspend time 15 s t ps program suspend time 10 s oe program cycle input data address a0 55 555 555 aa aaa t bp t wph t wp ce we a0 - a19 data t as t ah t dh t ds 555 aa t wc oe (1) aa 80 note 3 55 55 555 555 note 2 aa word 0 word 1 word 2 word 3 word 4 word 5 aaa aaa t wph t wp ce we a0-a19 data t as t ah t ec t dh t ds 555 t wc
22 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ?ac read characteristics? on page 18. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ?ac read characteristics? on page 18. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns a0-a19 we ce oe i/o7 tdh toeh toe high z an an an an an twr toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 50 ns t wr write recovery time 0 ns
23 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 software product identification entry (1) software product identification exit (1)(6) notes: 1. data format: i/o15 - i/o8 (don?t care); i/o7 - i/o0 (hex) address format: a11 - a0 (hex), and a11 - a19 (don?t care). 2. a1 - a19 = v il . manufacturer code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 001fh(x16) device code: 00c0h (x16) - bottom boot; 00c2h (x16) - top boot. 6. either one of the product id exit commands can be used. load data aa to address 555 load data 55 to address aaa load data 90 to address 555 enter product identification mode (2)(3)(5) load data aa to address 555 load data 55 to address aaa load data f0 to address 555 exit product identification mode (4) or load data f0 to any address exit product identification mode (4) sector lockdown enable algorithm (1) notes: 1. data format: i/o15 - i/o8 (don?t care); i/o7 - i/o0 (hex) address format: a11 - a0 (hex), and a11 - a19 (don?t care). 2. sector lockdown feature enabled. load data aa to address 555 load data 55 to address aaa load data 80 to address 555 load data aa to address 555 load data 55 to address aaa load data 60 to sector address pause 200 s (2)
24 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 psram description the pseudo-sram (psram) is an integrated memory based on a self-refresh dram array. the device is offered with a density of 8-mb it organized as 512,288 words by 16 bits. it is designed to be identical in operation and interface to the standard 6t srams. the device is designed for low standby, low operating current an d includes a user configurable low-power mode. two chip selects (p cs1 and zz ) and an output enable (p oe ) is available to allow for easy memory expansion. byte controls (p ub and p lb ) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. the deep sleep mode reduces standby current drain while not retaining data in the array. psram features fast cycle times ?t acc < 70 ns very low standby current ?i sb0 < 10 a @ 3.0v very low operating current ? 1.0 ma at 3.0 and 1 s (typical) memory expansion with pcs1 and p oe ttl compatible three-state output driver functional block diagram prech a rge circ u it clk gen pvcc pgnd memory arr a y row addre ss e s i/o circ u it col u mn s elect d a t a cont d a t a cont col u mn addre ss e s d a t a cont control logic oe we ub lb zz i/o 8 ~ i/o15 i/o0 ~ i/o7 row s elect pc s 1 p p p p
25 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 note: 1. x means don?t care (must be low or high state). notes: 1. t a = - 25 c to 85 c, otherwise specified. 2. overshoot and undershoot are sampled, not 100% tested. 3. overshoot: pv cc + 1.0v in case of pulse width < 20 ns. 4. undershoot: -1.0v in case of pulse width < 20 ns. note: 1. capacitance is sampled, not 100% tested. functional description pcs1 zz poe pwe plb pub i/o0 - 7 i/o8 - 15 mode power hhx (1) x (1) x (1) x (1) high-z high-z deselected standby x (1) lx (1) x (1) x (1) x (1) high-z high-z deselected low-power modes x (1) hx (1) x (1) h h high-z high-z deselected standby l hhhlx (1) high-z high-z output disabled active hhhx (1) l high-z high-z output disabled active lh lh lhd out high-z lower byte read active hlhigh-zd out upper byte read active lld out d out word read active x (1) l lhd in high-z lower byte write active hlhigh-zd in upper byte write active lld in d in word write active recommended dc operating conditions (1)(2) item symbol min max unit supply voltage pv cc 2.7 3.3 v ground pgnd 0 0 v input high voltage v ih 0.8 pv cc pv cc + 0.2 (3) v input low voltage v il -0.2 (4) 0.2 pv cc v capacitance (1) (f = 1 mhz, t a = 25 c) item symbol test condition min max unit input capacitance c in v in = 0v 8 pf i/o capacitance c i/o v in = 0v 8 pf
26 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 dc and operating characteristics item symbol test conditions min typ max unit input leakage current i li v in = pgnd to pv cc -1 1 a output leakage current i lo pcs1 = v ih , zz = v ih , poe = v ih or pwe = v il , v i/o = pgnd to pv cc -1 1 a average operating current i cc1 cycle time = 1 s, 100% duty, i i/o = 0 ma, pcs1 < 0.2v, zz = v ih , v in < 0.2v or v in > pv cc - 0.2v 13ma i cc2 cycle time = min, i i/o = 0 ma, 100% duty, pcs1 = v il , zz = v ih , v in = v il or v ih 25 ma output low voltage v ol i ol = 0.5 ma 0.2 pv cc v output high voltage v oh i oh = -0.5 ma 0.8 pv cc v standby current (ttl) i sb pcs1 = v ih , zz = v ih , other inputs = v ih or v il 0.3 ma standby current (cmos) i sb1 pcs1 > pv cc -0.2v, zz > pv cc - 0.2v, other inputs = 0 ~ pv cc 70 a low power modes i sb0 zz < 0.2v, other inputs = 0 ~ pv cc , no refresh (dpd) 10 a
27 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 ac characteristics (pv cc = 2.7v ? 3.3v, t a = -25 c to 85 c) parameter list symbol speed bins unit 70 ns min max read read cycle time t rc 70 40k ns address access time t aa 70 ns chip select to output t co 70 ns output enable to valid output t oe 25 ns pub , plb access time t ba 70 ns chip select to low-z output t lz 10 ns pub , plb enable to low-z output t blz 10 ns output enable to low-z output t olz 5 ns chip disable to high-z output t hz 0 5 ns pub , plb disable to high-z output t bhz 0 5 ns output disable to high-z output t ohz 0 5 ns output hold from address change t oh 5 ns write write cycle time t wc 70 40k ns chip select to end of write t cw 60 ns address set-up time t as 0 ns address valid to end of write t aw 60 ns pub , plb valid to end of write t bw 60 ns write pulse width t wp 50 ns write recovery time t wr 0 ns write to output high-z t whz 0 5 ns data to write time overlap t dw 20 ns data hold from write time t dh 0 ns end write to output low-z t ow 5 ns pcs1 high pulse width t cp 10 ns
28 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 power up sequence 1. apply power. 2. maintain stable power for a minimum of 200 s with pcs1 = v ih standby mode state machines standby mode characteristics mode memory cell data standby current (a) wait time (s) standby valid 70 (isb1) 0 low power modes invalid 10 (isb0) 200 initi a l s t a te s t a nd b y mode active mode power on pc s 1 = v ih (or/ a nd pub = plb = v ih ) zz = v ih pc s 1 = v ih pc s 1 = v il , z z = v ih pub or/ a nd plb = v il low power (d a t a inv a lid) w a it 200 s pc s 1 = v ih , zz = v il pc s 1 = v ih , z z = v ih zz = v ih pc s 1 = v ih , zz = v il pc s 1 = v ll
29 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 read cycle (1) (address controlled, pcs1 = poe = v il , zz = pwe = v ih , pub or/and plb = v il ) read cycle (2) (zz = pwe = v ih ) notes: 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max) is less than t lz (min) both for a given device and from device to device interconnection. 3. do not access device with cycle timing shorter than t rc (t wc ) for continuous periods > 40 s. addre ss d a t a o u t previo us d a t a v a lid d a t a v a lid a h addre ss a a e h lz z d a t a v a lid high-z hz pc s 1 pub, plb poe d a t a o u t
30 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 write cycle (1) (pwe controlled, zz = v ih ) write cycle (2) (pcs1 controlled, zz = v ih ) write cycle (3) (pub , plb controlled, zz = v ih ) notes: 1. a write occurs during the overlap (t wp ) of low pcs1 and pwe . a write begins when pcs1 goes low and pwe goes low with asserting pub or plb for single byte operation or simultaneously asserting pub and plb for double byte operation. a write ends at the earliest transition when pcs1 goes high and pwe goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the pcs1 going low to end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as pcs1 or pwe going high. 5. do not access device with cycle timing shorter than t rc (t wc ) for continuous periods > 40 s. addre ss pc s 1 pub, plb pwe d a t a o u t c w r w w p s high-z high-z d a t a undefined d a t a v a lid w w hz d a t a in (2) (1) (4) addre ss pc s 1 pub, plb pwe d a t a o u t c r w p high-z high-z d a t a v a lid w d a t a in w s w (2) (1) (4) addre ss pc s 1 pub, plb pwe d a t a o u t c r w p high-z high-z d a t a v a lid w d a t a in w w s (2) (1) (4)
31 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 deep power-down mode entry/exit t zzmin a4 pc s 1 pub, plb pwe c r w p zz zwe regi s ter write (dpd) deep power down s t a rt deep power down exit next cycle (2) (1) (4) parameter description min max units t zzwe zz low to write enable low 0 1 s t r (deep power-down mode only) operation recovery time 200 s t zzmin low power mode time 10 s
32 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 ordering information t acc (ns) voltage range ordering code flash boot block psram size package operation range 70 2.7v - 3.3v at52bc1661at-70ci top 8-mbit 66c5 extended (-25 to 85 c) 70 2.7v - 3.3v AT52BC1661A-70CI bottom 8-mbit 66c5 extended (-25 to 85 c) package type 66c5 66-ball, plastic chip-scale ball grid array package (cbga)
33 at52bc1661a(t) [preliminary] 3455a?stkd?11/04 packaging information 66c5 ? cbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 66c5 , 66-ball (12 x 8 array), 10 x 8 x 1.2 mm body, 0.8 mm ball pitch chip-scale ball grid array package (cbga) a 66c5 09/19/01 side view a a1 0.12 seating plane c c top view bottom view 0.60 ref e d a1 ball corner ?b marked a1 identifier a b c d e f g h 1 2 3 4 5 6 7 8 9 10 11 12 d1 1.20 ref e e e1 common dimensions (unit of measure = mm) symbol min nom max note e 9.90 10.00 10.10 e1 ? 8.80 ? d 7.90 8.00 8.10 d1 ? 5.60 ? a ? ? 1.20 a1 0.25 ? ? e 0.80 bsc ?b ? 0.40 ?
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